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Application Note 1283
S1 - POWER DOWN CONTROL
Once static observations check out, you can then increase
SPDT - CENTER OFF
R7
GND
10k
VDD
PD - BNC
power current limits for VCC/VH and apply higher frequency
inputs to the IN_A/IN_B pins.
Layout Information
GND
All evaluation boards have complete silk-screen information
regarding Test points, Jumpers and Component placements.
VDD 1
2
3
4
VDD
PD
IN-B
IN-A
OB
GND
VH
OA
8
7
6
5
Schematic Information
Schematics are drawn with physical location in mind. Any
ISL55110, ISL55111_TSSOP
FIGURE 2. TSSOP AND QFN EVALUATION BOARDS HAVE
THE SAME POWER DOWN CIRCUITRY
Finally the center off position provides a means of
connecting a repetitive signal source to the PD input. This is
so that the user can observe Power Down Enable/Disable
timing. An important note to remember when using the PD -
BNC: 1) Place the switch in Center-Off position. 2) The PD
input is referenced to VDD and ground.
changes in electrical circuitry will be updated in this
document as needed.
Included below are two schematics. ISL55110, ISL55111:
TSSOP dual driver device and ISL55110, ISL55111 QFN
dual driver. Both packages have the Power Down Control,
while the QFN has both Power Down and Enable inputs.
Driver Loads
EN - BNC
R7
10k
S2 - POWER DOWN CONTROL
SPDT - CENTER OFF VDD
PD - BNC
GND
DRIVER OUT OB
DIF+
DIF-
R3
0 Ω
C6
NOT
POPULATED
R5
0 Ω
C8
NOT
POPULATED
OB - BNC
S1- ENABLE CONTROL
SPDT- CENTER OFF
GND
GND
TP-OB
GND
GND
R8
10k
DRIVER OUT OA
DIF+
R4
0 Ω
R6
0 Ω
OA - BNC
V D D 1
2
3
4
VDD
/ENABLE
PD
IN-B
OB
GND
VH
OA
12
11
10
9
DIF-
TP-OA
C7 C9
NOT NOT
POPULATED POPULATED
GND
FIGURE 4. CUSTOM LOAD COMPONENTS
ISL55110, ISL55111_QFN
FIGURE 3. QFN PACKAGES HAVE BOTH POWER DOWN
AND OUTPUT ENABLE DIGITAL INPUTS
Initial Power Up
Please refer to the device specification for power up
sequencing and current requirements. Also note that the
frequency of operation of each driver will determine the
current needed. There are graphs in the specification
regarding current characteristics.
When first powering up the device, set all power bus inputs
to minimum current levels needed for quiescent operation.
Check the device out statically with DC inputs on the IN_A/
IN_B pins and observe that the OA/OB outputs toggle when
the Input pins rise above and below the logic thresholds.
Please note that these inputs are intended for use by high
speed logic. Avoid slow DC ramps.
VDD current should be ~3.6mA and VH should be less then
100μAmps with no DC loads on the outputs.
2
Component locations C6 to C7 and R3 to R6 are surface
mount locations provided so the user can experiment with
various load configurations.
AN1283.0
February 13, 2007
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